The human brain is significantly faster than even modern computers when it comes to performing intelligent information processing, such as image recognition, language comprehension or combinatorial optimization. Primarily, this is because of fundamental differences in the information processing architectures of computers and human brains. Most digital computers use sequential processing, while the human brain utilizes massively parallel computation. More specifically, the human brain comprises a dense network of numerous (approximately 10.sup.10) functionally simple logic elements--neurons--which are interconnected in varying strengths by an even larger number (approximately 10.sup.14) of still simpler interconnecting passive elements--synapses. This type of network configuration is now commonly referred to as a neural network architecture. Hormonal activity in the brain varies the effective weighting of the synaptic interconnections.
In recent years, considerable effort has been made to develop hardware--as opposed to software (or computer-controlled)--implementations of artificial neural network systems. These hardware systems attempt to simulate the massive parallelism of the human brain so that intelligent, associative information processing can be performed.
Hardware realizations of neural networks, to date, have been designed generally as illustrated by the N.times.N matrix of FIG. 1. The neurons are typically represented by simple thresholding amplifiers (A.sub.1, A.sub.2, A.sub.3 . . . A.sub.N) and the synapses take the form of a matrix of passive interconnecting elements, such as high-value switched resistors (R.sub.12, R.sub.22, R.sub.31, etc.). As shown in FIG. 1, the output voltage of each amplifier is fed back by way of resistive elements to its own input and to the input of each of the other amplifiers. A network having N amplifiers will, therefore, have as many as N.sup.2 resistive elements in the interconnecting matrix. Consequently, a large-scale hardware realization occupies an extensive semiconductor area, with as much as eighty to ninety percent of that area taken up by the massive interconnecting matrix.
Due to its flexibility, which accommodates fabrication in large sheets, non-crystalline silicon--such as hydrogenated amorphous silicon (a-Si:H)--has been used as the semiconductor platform for some of these hardware realizations, even though it does not conduct as well as crystalline silicon or gallium arsenide.
The passive nature of the synaptic (resistive) elements has precluded variable weighting in these prior neural implementations. In fact, the prior hardware implementations were typically fabricated by burning out resistive elements at predetermined locations in the interconnecting matrix. Consequently, no reversible (or variable) weighting of the synaptic interconnections has been possible and, therefore, the prior artificial implementations are only very limited simulations of natural neural network systems.